Contents

• Contents
• List of Tables
• Changes applied to this manual
• Important note
• Analog Signal Processing Architecture
  • Overview
  • The frontend (Helix2.1)
  • The comparator
  • The pipeline
  • The pipeline readout amplifier ("pipeamp")
  • The multiplexer
  • The current buffer
  • The analog receiver circuit
• Digital Control Circuitry
  • The pipeline and readout control logic
  • The bias current sources
  • The control voltage sources
  • The sampling clock generator
  • The starter circuit
  • The readout
    • Daisy chain mode
    • Failsafe daisy chaining with Helix128-3.0
    • TokenDelay
    • TransmitEnable
  • The synchronicity monitor
  • The test pulse circuit
  • The serial interface
  • Last but not least
    • FifoFull
    • MuxDisable
• Appendix: Pad Description
  • Front pads
  • Bottom pads
  • Rear pads
  • Top side pads
  • Core pads
• Appendix: List of Known Problems
  • Solved problems at Helix128-2.1
  • Solved problems at Helix128-2.2
  • Solved problems at Helix128-3.0
• References