Rear pads

The pads on the rear side of Helix128-2.x are placed in a 140$\mu$m pitch. A description of the pads of Helix128-2.0 is given in table 13 on page , of Helix128-2.1 in table 14 on page , and of Helix128-2.2 in table 15on page .

 

Ref. no. Pin name Type Description

240 Vddg supply positive pad guard supply voltage (+2V)

239,238 Vddd supply positive digital supply voltage +2V)

237-234 Vdda supply positive analog supply voltage (+2V)

233-230 Vssa supply negative analog supply voltage (-2V)

229,228 Vssd supply negative digital supply voltage (-2V)

227 Vssg supply negative pad guard supply voltage (-2V)

$$\Omega$$ 226 Rref output

225 IrefOut output output of internal reference current source

224 IrefIn input reference current input for internal current DAC; may either be connected to an external reference current source or to the IrefOut pin, if internal reference current source is to be used

223 Voffset blocking outp. should be connected to external blocking capacitor

222 Idriver ``

$$\gt 1\mu F$$ 221 Vdcl

$$\gt 1\mu F$$ 220 Vd

219 VcompRef ``

218 AnalogOutDummy output dummy serial analog output, should be subtracted from AnalogOut

217 AnalogOut output serial analog output

216,215 n. c. n.c. not connected

$$\langle \rangle$$ 214 213-209

$$\langle \rangle$$ 209 941 ``

208 FcsTp input digital test pulse input; the rising edge signals moment of charge injection

207 SufixReset active high reset signal for bias generator and controller part

206 notReset input active low pipeline reset signal

205 DataValid output active high signal indicating valid data on analogOutDummy and analogOut

204 Error output active high signal indicating an error condition on the chip

203 SerLoad input active high load signal for serial line interface

202 SerData input active high data signal for serial line interface

201 TrigIn input active high readout trigger input

200 SerClk input active high clock of serial line interface

199 Rclk input active high readout clock for data multiplexer

198 Sclk input active high sampling clock; the falling edge signals the sampling point of time

 

Ref. no. Pin name Type Description

240 Vddg supply positive pad guard supply voltage (+2V)

239,238 Vddd supply positive digital supply voltage (+2V)

237-234 Vdda supply positive analog supply voltage (+2V)

233-230 Vssa supply negative analog supply voltage (-2V)

229,228 Vssd supply negative digital supply voltage (-2V)

227 Vssg supply negative pad guard supply voltage (-2V)

$$\Omega$$ 226 Rref output

225 IrefOut output output of internal reference current source

224 IrefIn input reference current input for internal current DAC; may either be connected to an external reference current source or to the IrefOut pin, if internal reference current source is to be used

223 Voffset block. outp. should be connected to external blocking capacitor

222 Idriver block. outp. ``

$$\gt 1\mu F$$ 221 Vdcl block. outp.

$$\gt 1\mu F$$ 220 Vd block. outp.

219 VcompRef block. outp. ``

218 AnalogOutDummy output dummy serial analog output, should be subtracted from AnalogOut

217 AnalogOut output serial analog output

$$\langle \rangle$$ 216 215-211

$$\langle \rangle$$ 211 996 ``

210 FcsTp input digital test pulse input; the rising edge signals moment of charge injection

209 SufixReset active high reset signal for bias generator and controller part

208 notReset input active low pipeline reset signal

207 DataValid output active high signal indicating valid data on AnalogOutDummy and AnalogOut

206 Error output active high signal indicating an error condition on the chip

205 SerLoad input active high load signal for serial line interface

204 SerData input active high data signal for serial line interface

203 TrigIn input active high readout trigger input

202 SerClk input active high clock of serial line interface

201 notRclk input active low readout clock for data multiplexer

200 Rclk input active high readout clock for data multiplexer

199 notSclk input active low sampling clock; the rising edge signals the sampling point of time

198 Sclk input active high sampling clock; the falling edge signals the sampling point of time

 

Ref. no. Pin name Type Description

240 Vddg supply positive pad guard supply voltage (+2V)

239,238 Vddd supply positive digital supply voltage (+2V)

237-234 Vdda supply positive analog supply voltage (+2V)

233-230 Vssa supply negative analog supply voltage (-2V)

229,228 Vssd supply negative digital supply voltage (-2V)

227 Vssg supply negative pad guard supply voltage (-2V)

$$\Omega$$ 226 Rref output

225 IrefOut output output of internal reference current source

224 IrefIn input reference current input for internal current DAC; may either be connected to an external reference current source or to the IrefOut pin, if internal reference current source is to be used

223 Idriver blocking outp. should be connected to external blocking capacitor

222 VcompRef blocking outp. ``

221 Vd blocking outp. ``

220 Vdcl blocking outp. ``

219 Voffset blocking outp. ``

218 AnalogOutDummy output dummy serial analog output, should be subtracted from AnalogOut

217 AnalogOut output serial analog output

$$\langle \rangle$$ 216 input (int.

pulldown) [-1.5ex]active high chip id adress

$$\langle \rangle$$ 215 input (int.

pulldown) [-1.5ex] `` 214-211

$$\langle \rangle$$ 211 input (int.

pulldown) [-1.5ex] ``

210 FcsTp input digital test pulse input; the rising edge signals moment of charge injection

209 SufixReset active high reset signal for bias generator and controller part

208 notReset input active low pipeline reset signal

207 DataValid output active high signal indicating valid data on analogOutDummy and analogOut

206 Error output active high signal indicating an error condition on the chip

205 SerLoad input active high load signal for serial line interface

204 notTrigIn LVDS-input active low readout trigger input

203 TrigIn LVDS-input active high readout trigger input

202 n. c. n.c. Not connected

201 notRclk LVDS-input active low readout clock for data multiplexer

200 Rclk LVDS-input active high readout clock for data multiplexer

199 notSclk LVDS-input active low sampling clock; the rising edge signals the sampling point of time

198 Sclk LVDS-input active high sampling clock; the falling edge signals the sampling point of time