The sampling clock generator

 In the following we discuss the sampling clock Sclk ruling the pipeline operation. This clock should not be confused with the comparator's CompClk clock described in sect. 3.3 (both run at 10 MHz in the HERA-B experiment; both try to catch the maximum pulse height of the shaped frontend pulse but, however, the sampling transitions of the two clock should be slightly detuned to avoid mutual interference).

The falling edge of the sampling clock determines the sampling point of time, i. e. when the frontend outputs are sampled into the pipeline column ``on duty''. The sampling clock (nominally 10Mhz) Sclk can be either applied to the Sclk input pad or generated internally from Rclk. Therefore the lower four bits of the ClkDiv register hold the ratio of the Rclk (readout) and Sclk (sampling) clocks. Valid values are 0-15. If the content of ClkDiv = 0, the signal applied to the Sclk input pad is used for sampling. The internally generated Sclk will have its first rising edge synchronously with the fourth rising edge of Rclk following the rising edge of notReset. This behaviour is illustrated in Fig. 12. The duty cycle of the internally generated Sclk signal is 50%.

  

Figure 12: Sclk initialization for Clockdiv $\neq$ 0