The synchronicity monitor

The synchronicity monitor circuit checks the signals of neighbouring Helix128-2 chips to assure synchronous operation. For this purpose, internal signals TrigMon and WriteMon are generated when the write pointer resp. the trigger pointer passes by column 0 of the pipeline. The synchronicity monitor checks the simultaneous occurrence of these internal signals as well as of the DataValid signals with the ones received on SyncIn<i>. SyncOut<i> signals are generated depending on the comparison result according to table 3. The DataValid check, naturally, has to be abandonned in daisy chain operation mode.

Using a differential architecture both missing and wrong monitor pulses can be detected. If a deviation occurres, an error signal on Error is generated, which should be collected from the last chip in the synchronicity chain.

The content of the SyncCtrl register determines the behaviour of the SyncOut<0:5> and Error signals. A description is given in Tab. 4.

signal name logic dependency comment

SyncOut<0> !TrigMon & SyncIn<0> active low wired or of all TrigMon signals

SyncOut<1> TrigMon & SyncIn<1> wired and of all TrigMon signals

SyncOut<2> !writeMon & SyncIn<2> active low wired or of all TrigMon signals

SyncOut<3> writeMon & SyncIn<3> wired and of all writeMon signals

SyncOut<4> !DataValid & SyncIn<4> active low wired or of all DataValid signals

SyncOut<5> DataValid & SyncIn<5> wired and of all DataValid signals

caption

[Definition of SyncOut<5:0> signals] Dependencies of the SyncIn<5:0> and SyncOut<5:0> signals  

 

bit number function if cleared (0) function if set ( 1)

7 (MSB) Error pin in latch mode (i.e. signal remains high after occurrence of an error Error pin in transient mode (i.e. it becomes active only during the existence of an error condition)

6 Error signal is generated from Sync<0:1> (i.e. TrigMon) signals Sync<0:1> (i.e. TrigMon) is ignored for the Error signal

5 Error signal is generated from Sync<2:3> (i.e. WriteMon) signals Sync<2:3> (i.e. WriteMon) is ignored for the Error signal

4 Error signal is generated from Sync<4:5> (i.e. DataValid) signals Sync<4:5> (i.e. DataValid) is ignored for the Error signal

3 SyncOut<0:1> signal is generated from SyncIn<0:1> and TrigMon signals SyncOut<0:1> = SyncIn<0:1> (i.e. TrigMon of this Helix128-2 does not contribute to SyncOut<0:1>)

2 SyncOut<2:3> signal is generated from SyncIn<2:3> and WriteMon signals SyncOut<2:3> = SyncIn<2:3> (i.e. WriteMon of this Helix128-2 does not contribute to SyncOut<2:3>)

1 SyncOut<4:5> signal is generated from SyncIn<4:5> and DataValid signals SyncOut<4:5> = SyncIn<4:5> (i.e. DataValid of this Helix128-2 does not contribute to SyncOut<2:3>)

0 (LSB) Error = 0 (i.e. reset Error, only useful if bit #7 = 0) Error = 1 (i.e. set Error, only useful if bit #7 = 0)