HD-ASIC-33-0697

Helix128-x


User Manual

V2.1, 3.2.1999

Wolfgang Fallot-Burghardt, Edgar Sexauer, Ulrich Trunk

Max-Planck-Institut für Kernphysik, Heidelberg

Martin Feuerstack-Raible, Boris Glass

Physikalisches Institut der Universität Heidelberg, Heidelberg

Ruud Kluit

NIKHEF, Amsterdam

Contact:

Martin Feuerstack-Raible

ASIC Labor

Universität Heidelberg

Schröderstr. 90

D-69120 Heidelberg

E-Mail:feuersta@asic.uni-heidelberg.de

Tel: +49 6221 544957

Fax: +49 6221 544345

Abstract

Helix128-2 and its variants 2.1, 2.2, and 2.3 are analog readout chips for silicon microstrip detectors and microstrip gaseous chambers manufactured in the 0.8$\mu$m-CMOS process of AMS. The chips integrate 128 channels with low noise charge sensitive preamplifier/shapers whose outputs are sampled into an analog pipeline with a maximum latency of 128 sampling intervals. A pipeline readout amplifier, a fast 40MHz multiplexer and a 40MHz current buffer form the backend stages of the designs. Additionally, each channel is equipped with an AC-coupled comparator behind the preamplifier/shaper. All comparators share a common threshold, the output of four neighbouring comparators being ORed and brought offchip.

The bias settings and various other parameters are programmable via a serial line protocol. The chips also integrate some monitoring functionality and the ability to report error conditions.

The latest version is the Helix128-3.0, which will also be the final version for this chip family. On this chip, remaining bugs were fixed and it is additionaly equipped with a failsafe token scheme, which makes the chip useable in long daisy chains.