VeranstaltungenSeminare

Allgemeine Vorträge

Schaltungen und Methoden im VLSI Design

Sommersemester 2016

gehe zu Wintersemester 2015/2016   gehe zu Wintersemester 2016/2017
URL zum ICS-Kalender dieses Seminars

Seminarbox 1 (01.107)
mittwochs 16:00
Weekly seminar of the Heidelberg ASIC-Laboratory

23.3.2016 16:00
Design and Measurement of HICANN-DLS-2 Neuron
Syed Ahmed Aamir
Seminarbox 1 (01.107)
30.3.2016 16:00
Overview 10bit SAR ADC in TSMC 65nm
Korbinian Schreiber
Seminarbox 1 (01.107)
6.4.2016 16:00
Hands-On: Automated simulation and analysis using Python
Sebastian Billaudelle
Seminarbox 1 (01.107)
13.4.2016 16:00
Hands-On: Automated simulation and analysis using Python Part 2
Sebastian Billaudelle
Seminarbox 1 (01.107)
11.5.2016 16:00
Submission Readiness Review: KLauS 4
Dr. Wei Shen
Seminarbox 1 (01.107)
25.5.2016 16:00
ARQ stuff
Gaetan Deletoille
Seminarbox 1 (01.107)
8.6.2016 16:00
SC analog readout chain for HICANN-DLS
Gerd Kiene
Seminarbox 1 (01.107)
29.6.2016 16:00
HICANN-DLS: Potential post-signal driver problem
Timo Wunderlich
Seminarbox 1 (01.107)
6.7.2016 16:00
CADC for HICANN-DLS
Korbinian Schreiber
Seminarbox 1 (01.107)
13.7.2016 16:00
An asynchronous priority encoder for HICANN-DLS
Gerd Kiene
Seminarbox 1 (01.107)
20.7.2016 16:00
Synaptic depression and facilitation for HICANN-DLS
Sebastian Billaudelle
Seminarbox 1 (01.107)
10.8.2016 16:00
Wiring and connectivity with Cadence Virtuoso
Dr. Johannes Schemmel
Seminarbox 1 (01.107)
24.8.2016 16:00
Automated design exploration using VHDL testbenches and Modelsim
Vitali Karasenko
Seminarbox 1 (01.107)
24.8.2016 16:00
A random number generator for HICANN-DLS
Christian Pehle
Seminarbox 1 (01.107)
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