In the FACETS project the goal is a much higher integration density compared to the Spikey based system. Basically, the FACETS hardware model consists of a large number of ASICs containing the analog neuron and synapse circuits. Due to the high acceleration factor of about 104 compared to the biological real time the necessary communication bandwidth in-between these Analog Network Chips (ANC) can exceed 1011 neural events per second, each encoding the transmission of an action potential from one source neuron to a set of target neurons. To achieve this communication bandwidth we use wafer-scale integration. In this technology, the silicon wafers containing the individual chips are not cut into dies, instead, the chips are interconnected directly on the wafer. This method provides the necessary connection density. Wafer-scale integration is feasible because the neural computation paradigm allows us to fulfill the mandatory prerequisites: fault tolerance and low power consumption.