Electronic Vision(s) Group
Past Projects
The FACETS Neuromorphic Hardware
Neuromorphic Hardware
Single Chip System
The "Spikey" Chip
The "Spikey" chip is the first neuromorphic chip developed in the Electronic Vision(s) group. The temporal evolution of its neurons' 384 membrane potentials is governed by the conductance based leaky integrate and fire model (LIF). A capacitive membrane integrates the charge flowing through the different ion channels. If the membrane potential reaches a fixed threshold voltage, a spike generation process will be triggered. The synapses are conductance based, with realistic levels for their reversal potentials. The shortening of the membrane time constant in the case that the total synaptic conductance reaches the high-conductance region can therefore be studied with the chip. Also, the exponential decay of the synaptic conductance is part of the design. This is important for the transformation of information from the spatial into the temporal realm. Each neuron receives input from 256 synapses. Another important aspect is the statistical distibution of neural parameters. No two neurons are equal in nature; and this should be the case in an VLSI model. By looking closely at an analog circuit, it can be seen that this is also true for microelectronics. Fluctuations in the manufacturing process lead to parameter variations of each transistor, making it an individual as well. But we want to control these fluctuations to generate neural microcircuits with a known statistical distribution of their parameters. Therefore, each electronic neuron will contain several individually tunable parameters. Plasticity is the key to understand how the brain can adapt to its environment. One important aspect of plasticity discovered in the recent years is the 'spike time dependent plasticity'. In the spiking neural network chip each synapse measures the correlation between pre- and postsynaptic signal. These measurements are used to calculate changes in the synaptic weights. A simulation of an electronic neuron is shown below. The neuron has one regular input (shown in orange) with a few additional spikes coming in and one input representing random background activity. It can be seen that the activity of the regular input alone is not strong enough to lift the membrane potential above the threshold voltage. The random background activity increases the mean membrane conductance and therefore enhances the sensitivity of the neuron to the regular input.
The following picture shows the first working prototype of the spiking neural network chip realised in a 0.18 um CMOS technology:
A comparison of the membrane potential between the chip and a numerical simulation (performed by NEST) is shown below:
