Circuits and methods for VLSI design: Weekly seminar of the Heidelberg ASIC-Laboratory

We meet in the Seminarbox I (01.107) at the first floor at 16:00 s.t.

Talks

Sorry, no talks

Previous talks

24.06.2020

  • BrainScaleS EXTOLL - A Progress Overview - Tobias Thommes (Slides)

03.06.2020

  • Lowest-Energy operation of the HICANN-X ASIC: Testboard development Part IV - Dr. Maurice Guettler, Dan Husmann, Joscha Ilmberger

13.05.2020

  • Lowest-Energy operation of the HICANN-X ASIC: Testboard development Part III - Dr. Maurice Guettler, Dan Husmann, Joscha Ilmberger

06.05.2020

  • Lowest-Energy operation of the HICANN-X ASIC: Testboard development Part II - Dr. Maurice Guettler, Dan Husmann, Joscha Ilmberger

29.04.2020

  • Lowest-Energy operation of the HICANN-X ASIC: Testboard development - Dr. Maurice Guettler, Dan Husmann, Joscha Ilmberger

22.04.2020

  • Low-Power Inference Setup for HICANN-X - Joscha Ilmberger (Slides)

15.04.2020

  • Wafer-Scale without Wafer : the BrainScaleS FrankenStein Wafer Project - Dr. Maurice Guettler (Slides)

19.02.2020

  • Tapeout Review Analog Design Changes HX2 - Sebastian Billaudelle (Slides)

08.01.2020

  • Hicann-X-L2comm over JTAG: Serializer-independent Interconnects - Vitali Karasenko (Slides)

27.11.2019

20.11.2019

  • The state of the neuron - Sebastian Billaudelle (Slides)
  • Simulated Calibration and Testing of Neurons on HX - Philipp Dauer (Slides)

06.11.2019

  • Proposal and Design of Back Illuminated 3D Silicon Photomultiplier - Dr. Wei Shen (Slides)

23.10.2019

  • PCI-Express on Stratix10 Handson - Christian Pehle

09.10.2019

  • Near-term packaging options for Multi-Hicann-X operation - Dr. Johannes Schemmel

25.09.2019

  • 25. ASIC-Labor Jubilšum

07.08.2019

  • BrainScaleS Extoll Testing and inter-FPGA Spike-Communication - Tobias Thommes (Slides)

26.06.2019

  • HICANN-X Analog Results - Sebastian Billaudelle (Slides)

29.05.2019

  • On-chip calibration on HICANN-DLS - Aron Leibfried (Slides)

08.05.2019

  • Vendor-independent FPGA synthesis with Synplify - Dr. Mitja Kleider (Slides)

03.04.2019

  • Waiting for HICANN-X: Building an FPGA design to interface with an asynchronous co-Processor - Vitali Karasenko (Slides)

27.02.2019

  • The MuPix8 - a large scale HV-MAPS prototype - Jan Hammerich (Slides)

20.02.2019

  • General Design Flow in GF FDX 22nm - Tobias Markus (Slides)

23.01.2019

  • Presentation: Semi-automatic flip-chip bonder - Herr Vogel
  • Fineplacer user experience - Dr. Christian Kreidl (Slides)
 
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talks
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