Circuits and methods for VLSI design: Weekly seminar of the Heidelberg ASIC-Laboratory

We meet in the Zoom ASIC Seminar at 16:00 c.t.

If interested I send the Zoom link to you.

Talks

Sorry, no talks

Previous talks

26.10.2022

  • Novel circuit possibilities with silicon nanowires - Dr. Johannes Schemmel (Paper)

28.09.2022

  • Presentation Elmos Semiconductor SE - Dr. Achim Stellberger (Slides)

14.09.2022

  • First layout concepts for a novel SAR-ADC for neuromorphic hardware - Philipp Dauer (Slides)

20.07.2022

  • Latched Sense Amplifiers: Comparator Design for a SAR-ADC - Philipp Dauer (Slides)

13.07.2022

  • A review of classic neuromorphics: translinear circuits and the differential-pair integrator - Dr. Johannes Schemmel (Slides)

06.07.2022

  • Ultrafast neural networks for optical communication - Dr. Johannes Schemmel (Slides)

01.06.2022

  • Neue Verstärker und ADC-Schaltungen für neuronale Netze - Kamal Abdellatif, Milena Czierlinski, Philipp Dauer (Slides)

23.03.2022

  • Mupix11 and beyond - Dr. Heiko Augustin (Slides)

02.03.2022

  • Teststand extended: MixedSignal simulations & template repository for analog simulation - Philipp Dauer/Yannik Stradmann (Slides)

16.02.2022

  • ADC Design: The Challenges of designing a SAR-ADC - Milena Czierlinski/Philipp Dauer (Slides)

09.02.2022

  • Mixed Signal Design Flow for Pixelated ASIC - Dr. Wei Shen (Slides)

15.12.2021

  • Sub-nanosecond time measurement using inverter chains - Alexander Schmidt (Slides)

22.09.2021

  • Conductance-based synapses for BrainScaleS-2 (and other stuff) - Sebastian Billaudelle (Slides)

15.09.2021

  • Automated verification for the upcoming BrainScaleS-2 ASIC - Yannik Stradmann (Slides)

08.09.2021

  • How Graph Convolutional Networks bring the power of AI to Electronic Design Automation - Dr. Johannes Schemmel (Paper)

18.08.2021

  • Low-power parallel single-ended links for scale-up of neuromorphic hardware - Joscha Ilmberger

11.08.2021

  • Discussion/evaluation of results of timing characterization of large mixed-signal blocks with Liberate-AMS - Dr. Andreas Grübl

21.07.2021

  • Low-power Capacitor Arrays for Charge Redistribution SAR A/D Converter in 65nm CMOS (Paper)
  • Mixed-Signal Computing for Deep Neural Network Inference (Paper)
  • A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing (Paper)

14.07.2021

  • Presentation different CS-ADC variants - Dr. Johannes Schemmel (Slides)
  • Paper presentation: Compact 10b SAR-ADC - Sebastian Billaudelle (Paper)

23.06.2021

  • Design Readiness Review SUS65T5 - David Schimansky (Slides)

16.06.2021

  • First measurements KLauS6b - Dr. Konrad Briggl (Slides)

09.06.2021

  • Literature Seminar: "Memristive and CMOS Devices for Neuromorphic Computing" - Dr. Johannes Schemmel (Paper)

26.05.2021

  • Xilinx AI nodes and Versal architecture - Joscha Ilmberger

12.05.2021

  • ISSCC 21: in-memory computing - two paper presentations - part 4
    • 16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b of Precision for AI Edge Chips
    • 16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications https://doi.org/10.1109/ISSCC42613.2021.9365766

05.05.2021

21.04.2021

  • ISSCC 21: in-memory computing - two paper presentations - part 2

14.04.2021

07.04.2021

  • Bayesian logic in neuron refractory states - Johannes Weis

20.01.2021

  • Keyence Digital Microscope VHX-7000 presentation - Patricia Mohr

16.12.2020

  • A Short (Post) Submission Readiness Review "KLauS6b" - Dr. Konrad Briggl

02.12.2020

  • Thoughts on conductance-based synaptic input circuits - Sebastian Billaudelle

25.11.2020

  • Final Review: Frankensteinboard - Dr. Maurice Güttler

04.11.2020

  • HICANN-X: Large macro block timing characterization, first experiences - Dr. Andreas Grübl (Slides)

28.10.2020

21.10.2020

  • HICANN-X: Results from testing - the RTL-view part I

30.09.2020

  • ASICs for Photon Detection integrating Avalanche Diodes and CMOS Readout - Dr. Peter Fischer (Slides)

23.09.2020

  • Final design issues for the BSS-2 mockup-wafer: Project Frankenstein - Dr. Maurice Güttler

16.09.2020

  • Run2020: Overview of the latest submissions - Benjamin Weinländer (Slides)

19.08.2020

  • EXTOLL News - Tobias Thommes (Slides)

12.08.2020

  • Updates on the KLauS6 chip - Dr. Wei Shen (Slides)

22.07.2020

  • FPGA design for future HAGEN-mode operation of HICANN-X - Joscha Ilmberger (Slides)

16.07.2020

  • Review of first version of new HICANN-X board for single chip platform - Dan Husmann

24.06.2020

  • BrainScaleS EXTOLL - A Progress Overview - Tobias Thommes (Slides)

03.06.2020

  • Lowest-Energy operation of the HICANN-X ASIC: Testboard development Part IV - Dr. Maurice Güttler, Dan Husmann, Joscha Ilmberger

13.05.2020

  • Lowest-Energy operation of the HICANN-X ASIC: Testboard development Part III - Dr. Maurice Güttler, Dan Husmann, Joscha Ilmberger

06.05.2020

  • Lowest-Energy operation of the HICANN-X ASIC: Testboard development Part II - Dr. Maurice Güttler, Dan Husmann, Joscha Ilmberger

29.04.2020

  • Lowest-Energy operation of the HICANN-X ASIC: Testboard development - Dr. Maurice Güttler, Dan Husmann, Joscha Ilmberger

22.04.2020

  • Low-Power Inference Setup for HICANN-X - Joscha Ilmberger (Slides)

15.04.2020

  • Wafer-Scale without Wafer : the BrainScaleS FrankenStein Wafer Project - Dr. Maurice Güttler (Slides)

19.02.2020

  • Tapeout Review Analog Design Changes HX2 - Sebastian Billaudelle (Slides)

08.01.2020

  • Hicann-X-L2comm over JTAG: Serializer-independent Interconnects - Vitali Karasenko (Slides)
 
talks
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