|title||Device Variability in Synapses of Neuromorphic Circuits|
In this thesis, we worked with the HICANN neuromorphic chip, which is part of the BrainScaleS System. Its analog circuits underlie time-independent variations that occur during the manufacturing process; this effect is known as mismatch. It causes the analog neuron and its synapses to deviate from desired behavior. Each neuron in HICANN has 23 individual parameters, that allow to compensate those variations. We therefore can calibrate the neuron. The variation of the obtained parameters from trial to trial are significant and set the limit for the reachable precision. In this work we develop new calibration methods for the synaptic and membrane time-constants of the neuron and analyze the behavior of the synapse circuits using transistor-level simulations. We analyze the post-synaptic potential (PSP) curves to extract the time-constants by fitting a parameterized model of the PSP recorded from the neurons. The resulting time-constant calibration improves the precision by which the model parameters can be set towards the mentioned limit. Monte Carlo transistor-level simulations are used to show that the relative deviation of the synaptic strength is below 10 % for most of its parameter range. The presented calibration vastly improves the usage of the analog neuron as a leaky integrate and fire model.