|author(s)||Matthias Hock, Andreas Hartel, Johannes Schemmel, Karlheinz Meier|
|title||An analog dynamic memory array for neuromorphic hardware|
|Keywords (shown)||analogue storage;content-addressable storage;mixed analogue-digital integrated circuits;neural chips;ramp generators;analog dynamic memory array;analog voltages;content-addressable memory;highly-configurable large-scale neuromorphic hardware;mixed-signal low-power process;power consumption;size 65 nm;voltage ramp generator;Arrays;Capacitors;Hardware;Logic gates;Programming;Radiation detectors;Transistors|
|source||Circuit Theory and Design (ECCTD), 2013 European Conference on|
We describe an array of capacitor based cells capable of storing analog voltages and currents for highly configurable large-scale neuromorphic hardware. A novel refresh scheme based on content-addressable memory as well as a slow and simple voltage ramp generator is presented. The circuits have been simulated in a 65nm mixed-signal low power process. Key characteristics are an area consumption of 175 μm2 and a power consumption of less than 125nW per stored value. A prototype chip has been designed and submitted for fabrication.