|author(s)||Bernhard Kaplan, Daniel Brüderle, Johannes Schemmel and Karlheinz Meier|
|title||High-Conductance States on a Neuromorphic Hardware System|
|Keywords||high-conductance states, neuromorphic hardware, VLSI neurons, membrane dynamics, spike-based conductance test|
|source||Proceedings of International Joint Conference on Neural Networks, Atlanta, Georgia, USA, June 14-19, 2009|
Under typical synaptical stimulation, cortical neurons exhibit a total membrane conductance which, compared to a situation without any input spikes, is signiﬁcantly increased. This results in a shorter membrane time constant and thus in an increased capability of the neuron to detect coincidences in its synaptic input. For this study, a neuromorphic hardware device was utilized, which does not provide direct access to its membrane conductances. Motivated by the aim of ﬁnding biologically realistic conﬁguration regimes for the chip operation, a purely spike-based method for the estimation of membrane conductances is presented, allowing to test the hardware membrane dynamics. A proof of principle is given by pure software simulations. Hardware results are presented which illustrate the functionality of the method and show the possibility to generate high-conductance states in the utilized VLSI1 neurons. In the ﬁnal section, limits and useful implications of the proposed method are discussed.