||J. Fieres, J. Schemmel, K. Meier
||A convolutional neural network tolerant of synaptic faults for low-power analog hardware
||Artificial Neural Networks, Pattern Recognition, Fault Tolerance, Hardware Implementation
||Proceedings of 2nd IAPR International Workshop on ArtificialNeural Networks in Pattern Recognition (ANNPR 2006), Springer LectureNotes in Artificial Intelligence 4087, 122--132 (2006)
||Recently, the authors described a training method for a convolutional neural network of threshold neurons. Hidden layers are trained by by clustering, in a feed-forward manner, while the output layer is trained using the supervised Perceptron rule. The system is designed for implementation on an existing low-power analog hardware architecture, exhibiting inherent error sources affecting the computation accuracy in unspecified ways. One key technique is to train the network on-chip, taking possible errors into account without any need to quantify them. For the hidden layers, an on-chip approach has been applied previously. In the present work, a chip-in-the-loop version of the iterative Perceptron rule is introduced for training the output layer. Influences of various types of errors are thoroughly investigated (noisy, deleted, and clamped weights) for all network layers, using the MNIST database of hand-written digits as a benchmark.