Beetle 1.0

Beetle 1.0 is the first prototype of the complete readout chip for the LHCb experiment. Its main purpose is evaluation of the concept and enabling system tests. Hence, while featuring the basic fast readout mode for LHCb (pipeline latency of 16- clock cycles, 16 multi-event buffers, output of analogue data via 4 ports at 40MHz speed) many other features are not yet implemented, especially the logic is not yet robust against SEU.

Layout and pad layout of the Beetle 1.0

Beetle 1.0 chip on a test PCB

Register map

The following table shows the register map of the chip. All registers are writeable and readable.