BeetleCO 1.0

Design of a comparator in a 0.25um CMOS technology (NIKHEF)

A comparator for the LHCb readout chip, the Beetle, has been designed in a 0.25um CMOS technology and is sent for fabrication. To improve threshold uniformity, each comparator has a 3 bits DAC. The comparator can handle positive and negative input signals. A polarity signal changes the polarity of the threshold level and makes the output signal always active high. The output signal is latched by a 40MHz clock and is selectable between time-over-threshold mode (in 25ns bins) and one pulse mode (25ns).

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Measurements with BeetleCO 1.0

• Measurements of analogue output driver (pdf)
• Investigation of characteristics and radiation hardness of the BeetleCO10 chip (LHCb 2001-037)