|author(s)||Johannes Schemmel, Daniel Bruederle, Karlheinz Meier, Boris Ostendorf|
|title||Modeling Synaptic Plasticity within Networks of Highly Accelerated I&F Neurons|
|source||Proceedings of the 2007 IEEE International Symposium on Circuits and Systems, New Orleans, USA|
When studying the different aspects of synaptic plasticity, the timescales involved range from milliseconds to minutes, thus covering at least seven orders of magnitude. To make this temporal dynamic range accessible to the experimentalist, we have developed a highly accelerated analog VLSI model of leaky integrate and fire neurons. It incorporates fast and slow synaptic facilitation and depression mechanisms in its conductance based synapses. By using a 180 nm process 10^5 synapses fit on a 25 mm^2 die. A single chip can model the temporal evolution of the synaptic weights in networks of up to 384 neurons with an acceleration factor of 10^5 while recording the neural action potentials with a temporal resolution better than 30 us biological time. This reduces the time needed for a 10 minute experiment to merely 6 ms, paving the way for complex parameter searches to reproduce biological findings. Due to a digital communication structure larger networks can be built from multiple chips while retaining an acceleration factor of a least 10^4.