• News
• EDA Administration
• Misc
  • Modules usage
  • Cadence ISCAPE
  • How to print your Cadence layout in A0
  • LVS with a GDS2 file and a verilog netlist
  • Mentor's Calibre in Cadence
  • Commandline DRC/Extract
  • Commandline LVS
  • Mixed Signal Simulation
  • Generate abstract
  • Setup the AMIS HK
  • HSpice MT
  • Usage of the FlexLM utils
  • How Monte Carlo Analysis Works
  • How to use DRACULA DRC
• Downloads (internal)
• Chipdatabase
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Here you find a few tutorials and code snippets

• Dracula How To (Not released to the public)
• Testreport for Europractice Submission
• .cdsplotinit File for Cadence, save to $CDSDIR/tools/plot
• How to print posters (A0 format)
• Calibre in Virtuoso (Not released to the public)
• How to start DRACULA DRC/Extract from commandline
• How to start DIVA LVS from commandline
• How to make a abstract from layout
• How to make LVS with a GDS2 file and a verilog netlist with CALIBRE
• Software for the HP82000
• HPIB commands for the HP82000
• Setup the AMIS HK
• HSpice with MT feature
• PDF for force umount on HPUX
• Usage of the FlexLM lmutil