HOME
Past Projects
FACETS (2006–2010) & FACETS-ITN (2009–2013)
Neuromorphic Hardware
Waferscale Integration System
Waferscale Integration Methods
Wafer Postprocessing
To test the feasibility of the choosen post processing method a custum made wafer has been produced. The so called test wafer does not contain any active structures. But it provides the necessary pads for the post processing. The following picture shows the test wafer without post processing.
Electronic Visions Group – Prof. Dr. Johannes Schemmel
Im Neuenheimer Feld 225a
69120 Heidelberg
Germany
phone: +49 6221 549849
fax: +49 6221 549839
email: schemmel(at)kip.uni-heidelberg.de
How to find us
