Helix128 Documentation


Helix128 is an analog readout chip for silicon microstrip detectors and microstrip gaseous chambers manufactured in the 0.8um-CMOS process of AMS. Helix128 integrates 128 channels with low noise charge sensitive preamplifier/shapers whose outputs are sampled into an analog pipeline with a maximum latency of 128 sampling intervals. A pipeline readout amplifier, a fast 40MHz multiplexer and a 40MHz current buffer form the backend stages of the design. Additionally, each channel is equipped with an AC-coupled comparator behind the preamplifier/shaper; all comparators share a common threshold, the output of four neighbouring comparators being ORed and brought offchip.

User manual

The manual is available
  • as a Gnu-Zipped Postscript file
  • as online HTML documentation




    Measurements with different versions of the chip were performed and the results are partly available via WWW.
  • Gain and pulse shape as a function of the load capacity (from Padova)
  • Gain at 20pF for different shaping times. (from Padova)
  • What happens to the channels close to one which is pulsed (from Padova)?
  • Various Measurements performed by NIKHEF (e. g. power consumption and pulse shape as a function of irradiation dose) are shown here.
  • Pulse shape versus irradiation dose
  • Power consumption versus irradiation dose
  • Homogenity of the analog pipeline signal
  • Crosstalk of the comparator: A pulse shape scan was performed by shifting the phase of a test signal relative to the phase of the clock that determines sampling time into the pipeline (i. e. Sclk). By means of this measurement crosstalk of the comparator's switching noise can be observed. We are currently working on this subject.
  • Crosstalk of comparator to analog (on Helix-PCB)
  • Pulse shapes of Helix128 at various bias settings and external loadsNew!



    Results of series tests

    Several wafers were produced so far. Our recent test procedure performed at the HP82000 chip tester in the ASIC laboratory and the results of it are described at two locations:

    Employment in systems

    Several groups are in the process of employing the Helix128 in detector readout systems, mainly for use at experiments at the HERA accelerator at DESY in Hamburg, germany.
  • The HERA-B Inner Tracker (see here for a link at the Inner Tracker group at DESY) uses the Helix chip to read out MSGC (MicroStrip Gaseous Chambers). In this system the chip is bonded directly on a multilayer PCB called Helix-PCB. The connection of the chip to the detector is done via a thinfilm ceramic, which integrates a fanin to translate from the detector readout pitch of 300um to the chip input pitch of 41um and also integrates resistors that form, together with the on chip input protection diodes, a protection against HV sparking of the chamber.
  • The HERA-B Vertex detector is read out by the Helix. The 50um readout pitch of the detector determines the pitch of the Helix chip. 10 Helix chips are mounted on a ceramic and the connection to the detector is done via a flex jumper.
  • The ZEUS experiment at DESY will use the Helix chip for reading out their new micro vertex detector. For this reason the ASIC laboratory Heidelberg now works in close collaboration with the groups involved in this projects, as there are DESY in Hamburg, NIKHEF in Amsterdam, netherlands, and university of Padova in italy. Independant measurements performed by this group are available. Also, they develop a failsafe token scheme for the daisy chained readout mode of the chip which will be included in a future version.



    Talks and presentations

  • Transparencies of Ulrich Trunk's talk given at the DPG98 in Freiburg, Germany

  • Review of the Helix' trigger functionality

    Preparatory document (gnu-zipped postscript)

    Last changes: 99/10/09 by Martin Feuerstack-Raible

    If you have comments or suggestions, email Ulrich Trunk