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Digital Learning System


A compelling argument for neuromorphic spike-based emulation can be made when considering that learning (in particular, the simulation of synaptic plasticity) is by far the most time-consuming factor in simulations. Especially since it is one of the essential properties of neurons and synapses is that they can change over time, in particular as a result of learning. In the newly developed HICANN-DLS chip, we use an on-chip plasticity processing unit (NUX, see publications below, github) to control that change. The prototype chip features an array of 32 x 32 synapses, each of which stores a 6 Bit weight and analog correlation traces that relate pre- and postsynaptic events. The plasticity processor can use that information to implement various plasticity rules, with STDP being just one example. To allow scaling of this hybrid analog/digital approach, NUX has a vector unit with direct access to the analog and digital state of all synapses that can access up to 16 synapses of one row in parallel. The analog parameter storage (see publications below) used to configure and calibrate the neurons can also be controlled by the plasticity processor.

Hicann-DLS is a novel device that emulates spiking neural networks with physical models of neurons and synapses implemented in analog microelectronics. Networks on this chip are emulated approximately 1000-fold faster than biological real-time.

Further details

  • Demonstrating Hybrid Learning in a Flexible Neuromorphic Hardware System, Arxiv Link

    Simon Friedmann, Johannes Schemmel, Andreas Gruebl, Andreas Hartel, Matthias Hock, Karlheinz Meier

    Publication has been submitted to IEEE Transactions on Biomedical Circuits and Systems

    Abstract: We present results from a new approach to learning and plasticity in neuromorphic hardware systems: to enable flexibility in implementable learning mechanisms while keeping high efficiency associated with neuromorphic implementations, we combine a general-purpose processor with full-custom analog elements. This processor is operating in parallel with a fully parallel neuromorphic system consisting of an array of synapses connected to analog, continuous time neuron circuits. Novel analog correlation sensor circuits process spike events for each synapse in parallel and in real-time. The processor uses this pre-processing to compute new weights possibly using additional information following its program. Therefore, learning rules can be defined in software giving a large degree of flexibility. Synapses realize correlation detection geared towards Spike-Timing Dependent Plasticity (STDP) as central computational primitive in the analog domain. Operating at a speed-up factor of 1000 compared to biological time-scale, we measure time-constants from tens to hundreds of micro-seconds. We analyze variability across multiple chips and demonstrate learning using a multiplicative STDP rule. We conclude, that the presented approach will enable flexible and efficient learning as a platform for neuroscientific research and technological applications.

  • Implementation and Characterization of Mixed-Signal Neuromorphic ASICs, Institute's Library

    Andreas Hartel, Dissertation

  • An analog dynamic memory array for neuromorphic hardware, Institute's Library

    Matthias Hock, Andreas Hartel, Johannes Schemmel, Karlheinz Meier

    Abstract: We describe an array of capacitor based cells capable of storing analog voltages and currents for highly configurable large-scale neuromorphic hardware. A novel refresh scheme based on content-addressable memory as well as a slow and simple voltage ramp generator is presented. The circuits have been simulated in a 65nm mixed-signal low power process. Key characteristics are an area consumption of 175 μm2 and a power consumption of less than 125nW per stored value. A prototype chip has been designed and submitted for fabrication.

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Last update of this page: 2016-01-03 by Andreas Hartel