Minutes and Results of the "Beetle User Review" Heidelberg 19. Dec. 2001 Present: Eddy Jans, Martin van Beuzekom, Hans Verkoojen, Yuri Ermoline, Achim Vollhardt, Nigel Smale, Christian Bauer, Michael Schmelling, Karl-Tasso Knoepfle, Werner Hofmann, Daniel Baumeister, Sven Loechner, Ulrich Trunk. Changes for Beetle 1.2 ====================== Digital Part ============ -DataValid: The position of dataValid with respect to the analogue data is according to Yuri of no belonging. Important is a "gap" (>=25ns) in the signal in case of consecutive readouts to determine the start of a new data burst. -DaisyChain/I2C Id.: The maximum number of chips on a I2C bus is 27 in the IT (Achim). For the VELO it is 16. For the IT a hardwired I2C Id is preferrable, while DaisyChain readout is not requested or used in LHCb. However Tasso Knoepfle insisted to keep the DaisyChain readout for convenience in test beam or lab applications. A fail-safe schema is not required. -ErrorFlags in the readout header: - 1 error bit for SEU in the comparator-shift-reg. - 1 error bit for SEU in the TP reg. bits - 1 parity bit for the PC# (Yuri) - 1 start bit (Yuri + Nigel) -Pads: Zurich and NIKHEF reported I2C problems depending on clock speeds and cable lengths. -> SDA and SCL pads will be equiped with schmitt triggers to overcome these. Pad positions: spatial separation of Sclk and I2C pads was proposed. The analogue outputs should be surrounded only by static signals (blocking, power supply) and not located on a chip corner. The token pads for the DaisyChain readout are among the top and bottom pads and carry CMOS signals. -Front Ends: The little confusion between NIKHEF an Heidelberg regarding bias currents was ruled out: Heidelberg values are strictly calculated from DAC settings, whie NIKHEF ones were callibrated from the measured power consumption. The set V and VI front ends can be operated with a bias up to Ipre=600uA Achim measured peaking times of 25..30ns with a Beetle 1.1 bonded to a detector (approx. 10..15pF) Daniel showed that there is no difference in the pulse shape of the test channel and sampling on Beetle 1.1. -Saturation: According to Sven no problem on the FE 1.1 (NMOS input). Hans doubted that and showed his own simulations, which show problems. These have to be verified with the actualFE schematic. Ulrich proposes to check the new FEs for saturation experimentally. NIKHEF proposes FE-measurements with a Si-detector. -Standard Bias Settings: It was agreed that Heidelberg provides standard settings which are included here: Beetle 1.1, also Beetle FE1.0 Beetle CO Beetle MA via Beetle BG (in [uA] and [mV]): "Flat baseline" settings: A B C D Ipre 600 350 320 346 Isha 80 120 31 63 -------------------------------------------- Ibuf 80 <- <- <- Vfp 0 <- <- <- Vfs 0 <- <- <- Icomp 100 <- <- <- Isf 300 <- <- <- Ipipe 100 <- <- <- Ivoltbuf 700 <- <- <- Vdc 1630 <- <- <- Vdcl 860 <- <- <- Default settings: Vdc 1000 Vdcl 1140 others as above BeetleFE 1.1: Ipre Isha Ibuf Vfp Vfs Set1/1 (FEin< 0>: 600 / 80 / 80 / 0 / 0 Set1/2 (FEin< 1>: 600 / 80 / 80 / 0 / 0 Set2/1 (Fein< 2>: 600 / 80 / 80 / 0 / 0 Set2/2 (Fein< 3>: 600 / 80 / 80 / 0 / 0 Set2/3 (Fein< 4>: 600 / 80 / 80 / 0 / 0 Set2/4 (Fein< 5>: 600 / 120 / 80 / 0 / 500 Set2/5 (Fein< 6>: 600 / 120 / 80 / 0 / 500 Set3/1 (Fein< 7>: 600 / 80 / 80 / 0 / 0 Set3/2 (Fein< 8>: 600 / 80 / 80 / 0 / 0 Set3/3 (Fein< 9>: 600 / 80 / 80 / 0 / 0 Set3/4 (Fein<10>: 600 / 120 / 80 / 0 / 500 Set3/5 (Fein<11>: 600 / 120 / 80 / 0 / 500 BeetleFE 1.2: Ipre Isha Ibuf Vfp Vfs Set2/1 (FEin< 0>: 300 / 100 / 80 / 0 / 0 Set5/1 (Fein< 1>: 300 / 80 / 80 / 0 / 0 Set5/2 (Fein< 2>: 300 / 80 / 80 / 0 / 0 Set5/3 (Fein< 3>: 300 / 80 / 80 / 0 / 0 Set5/4 (Fein< 4>: 300 / 80 / 80 / 0 / 0 Set5/5 (Fein< 5>: 300 / 80 / 80 / 0 / 0 Set5/6 (Fein< 6>: 300 / 100 / 80 / 0 / 0 Set5/7 (Fein< 7>: 300 / 80 / 80 / 0 / 0 Set5/8 (Fein< 8>: 300 / 100 / 80 / 0 / 0 Set5/9 (Fein< 9>: 300 / 80 / 80 / 0 / 0 Set6/1 (Fein<10>: 300 / 80 / 80 / 1000 / 0 Set6/2 (Fein<11>: 300 / 80 / 80 / 0 / 0 NIKHEF has to recallibrate their settings for consistency with other results. -ENC: Heidelberg results are 800e + 41e/pF, NIKHEF results are 700e + 45e/pF, which are rather consistent. According to NIKHEF simulations there is a large contribution of the bias generator to the ENC, which has to be verified. Tasso Knoepfle proposed to collect all noise measurements (and procedures) on a protected web page. -AnalogerOutput: Ulrich showd the schematic of a fully differential driver. NIKHEF and Zurich insisted on a higher gain: at least 2x, better more. -TP mask register: 1 bit / channel. Implementation has to be clarified: Shift register or 16 individual registers. -Comparator: Hans presented his measurement setup. However, only the principle was tested, and more than one chip has to be characterized. Tasso Knoepfle proposed to compare the (prompt) LVDS signals with the (sampled) analoge values. MPI people requested an adjustaple low pass filter for CM suppression. An additional VDAC will accomplish this. Hans reported a problem with small offset voltages on the comparator inputs, which are not yet understood. As a cure he proposed a current source to introduce a negative offset which can be easily corrected by the existing correction circuit. The comparator register will be split into the actual comparator registers and mask register(s) to prevent the unnecessary download of SEU-protected data. -Reset: A power-up reset will be included. It resets all registers. Soft- and hard-reset will be merged into a single (LVDS) reset signal, which only resets the pipeline control and leaves the registers untouched. -low trigger rate problems: The detected spikes result from the MUX and are well understood. As well als the timing of the "hold" switch, which caused the problem. Both will be changed. Tasso Knoepfle requested to check the complete circuit for "temorarily floating" lines. -Comp fanin/out: High impedance causes "crosstalk" into the next BX. Will be fixed by Hans. -bug fixes (ordert by priority): 0 modify protection diodes 1 sync trigger with clock reset "syncToken" circuit require a reset to activate latency changes readout within 900ns hard wired I2C addr. new pad positions and power routing (also for comp, consq. of hard wired I2C addr.) MUX switches & control (fixes low trigger rate probs.) change in Vd/Vdcl biasing power-up reset include error flags in PC# include comparator mask register [Hans] split compCtrl register (main / channel) 2 include Schmitt trigger in SDA/SCL pads modified analogue output current driver implement adjustable comparator time constant 3 modify fan-in/-out between comparator and pipeline [Hans] 4 include test pulse mask register ? fix comparator offsets [Hans] delayed include new front end (more results from new FEs required) -Not yet understood problems: All related to the FE! inconsistent rise time and remainder noise (higher than expected) channel-channel variations PC# dependency of noise -> all to be discussed on a FE(noise)-workshop (end of Jan.) -It has to be clearified if we can retreat from the submission and