FPL 2008
The 18th INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS
Heidelberg, Germany, September 8 - 10, 2008
http://fpl.org
Heidelberg, Germany, September 08-10
 

Industrial Workshops

 

Wednesday, September 10, 2008
14:00
Synplicity
Synopsys, Inc. - Synplicity Business Group Presents a Technical Seminar:
Prototyping as a Productive Verification Methodology

FPGA-based Prototyping has become a mandatory step for successful ASIC/ASSP and SoC design. The use of FPGAs for ASIC or SoC design verification is no longer the "ad-hoc / assembly required" methodology it once was; It has evolved into a truly productive and high-performance ASIC verification solution.
What should you consider when deploying an FPGA-based prototyping system? And, what are the necessary steps involved in getting an ASIC design to work on an FPGA-based prototyping board? You will learn this and more during this FREE technical and educational seminar.

What You Will Get

- A closer look at the HAPST architecture and capabilities; System set-up and configuration; Getting the most out of a prototyping system.
- Live demonstrations of the complete flow:
  - Preparing the ASIC design for prototyping
  - Designing partitioning and implementation
  - Prototyping system configuration and bring-up
  - Debugging the design and fixing errors

Presenter: Antti Innamaa - Synplicity

Antti is based in Synplicity's Helsinki site and is a Filed Application Engineer with a deep history of FPGA Prototyping.Prior to joining Synplicity, Innamaa was at the Nokia Research Centre in Helsinki for nearly four years, focusing on FPGA design and ASIC prototyping. Antti has a Master of Electrical Engineering (MEng) degree from Imperial College in London and he has presented part of his FPGA Prototyping work at previous SoC events.

Technical Seminar Flyer: here

Registration: http://www.synplicity.com/events/protosyncol_2008/register.html

14:00
Xilinx
Xilinx, Inc.
Introduction to PlanAhead and Partial Reconfiguration

This workshop will show how Xilinx PlanAhead software tool can increase design performance and achieve repeatable performance.  Topics include: Product Overview, Synthesis and Project Tips, Design Analysis, Creating a Floorplan, Improving Performance, and Partial Reconfiguration.

Presenter: Parimal Patel - XUP Senior Systems Engineer

Registration: http://www.xilinx.com/univ/xup/workshops/uwkshp.htm

14:00
MathWorks
MathWorks
Demonstration of a top-down design flow for implementing hardware and software systems

Model-Based Design as a development methodology allows designers of embedded systems to address the increasing number of challenges faced during the development cycle, such as:
- shorter design cycles (continuously rising requirements on productivity)
- increasing complexity of systems
- rising requirement of communication between different domains of knowledge (eg. analog/digital)

Initial algorithmic ideas can be developed and interchanged in an abstract manner using an executable specification in the form of a simulation model. This model is then refined in a step-by-step manner in order to include the effects that a real-world implementation may require. Architecture-specific aspects of the system, such as the bit and cycle accurate behaviour can be modelled and decisions on system architecture, such as partitioning, can be made on the basis of the effects seen in the simulations. Automatic C and HDL code generation tools enable a quick and error-free conversion of a model to implementable software and hardware. This provides designers with a toolchain that covers the complete development process, in which quick iterations from abstract initial ideas down to real-world implementations can be made. Thus, errors that are introduced into the development cycle during the specification phase, and, in a traditional development flow, that would have been found and corrected only in the final implementation phase, can now be uncovered and corrected earlier.

In this workshop, we will demonstrate the Model-Based Design development flow on the basis of a common image processing algorithm (Sobel Edge Detection). We will show the creation of an executable specification, the various stages of architecture-specific refinements, and the actual generation of HDL code that can be used for implementation purposes on an FPGA/ASIC.

Registration online at: http://www.mathworks.de/company/events/seminars/seminar18442.html or at the conference registration counter.

17:00CLOSE

 

Thursday, September 11, 2008
09:00
Xilinx
Xilinx, Inc.
Embedded Systems Design and Partial Reconfiguration (part 1 of 2)

This workshop brings experienced FPGA designers up to speed on the capabilities and characteristics of Xilinx processors. Time will be spent learning the steps of the Xilinx embedded design flow from system design to bitstream generation, and how the various tools in the Xilinx Embedded Development Kit (EDK) encompass these steps.  Attendees will get the chance to learn these steps through a series of hands-on lab exercises, as well as perform on-chip hardware/software verification. The experience is extended to Partial Reconfiguration designs using Xilinx PlanAhead and EDK software.  A demo will be provided illustrating how EDK, PlanAhead, and ISE can be used to carry out a partial reconfiguration design.

Presenter: Parimal Patel - XUP Senior Systems Engineer

Registration: http://www.xilinx.com/univ/xup/workshops/uwkshp.htm

17:00CLOSE

 

Friday, September 12, 2008
09:00
Xilinx
Xilinx, Inc.
Embedded Systems Design and Partial Reconfiguration (part 2 of 2)

This workshop brings experienced FPGA designers up to speed on the capabilities and characteristics of Xilinx processors. Time will be spent learning the steps of the Xilinx embedded design flow from system design to bitstream generation, and how the various tools in the Xilinx Embedded Development Kit (EDK) encompass these steps.  Attendees will get the chance to learn these steps through a series of hands-on lab exercises, as well as perform on-chip hardware/software verification. The experience is extended to Partial Reconfiguration designs using Xilinx PlanAhead and EDK software.  A demo will be provided illustrating how EDK, PlanAhead, and ISE can be used to carry out a partial reconfiguration design.

Presenter: Parimal Patel - XUP Senior Systems Engineer

Registration: http://www.xilinx.com/univ/xup/workshops/uwkshp.htm

17:00CLOSE