Distributed HAGEN Hardware

Core of the NATHAN module is the Xilinx Virtex-II Pro FPGA. It features a sufficient amount of configurable logic to run the low level parts of the training algorithms and native LVDS IOs with a maximum data rate of 800Mbps to utilize the full digital bandwidth of the HAGEN chip. Besides the HAGEN interface, two SMT connectors have been provided to accept daughter cards with future neural network chips. All neccessary support circuitry like current and voltage references is located in a shielded analog area of NATHAN.

Furthermore, the Virtex-II Pro offers enough configurable IOs and logic to connect to a DDR-SDRAM module and two SRAM chips. Each RAM bus has a data width of 64Bit. The utilized socket accepts standard SODIMM memory modules with capacities up to 1GB, whereas the SRAM chips are directly soldered on the NATHAN PCB and offer an overall capacity of 1MB.

The most outstanding features of the Virtex-II Pro are a built in 400MHz IBM PowerPC processor and up tp eight 622Mbps to 3.125Gbps full duplex serial transceivers. Four of these Multi-Gigabit Transceivers (MGTs) are routed over a differential high speed connector down to the backplane. The hard wired cross linking forms a 2D Torus that is being mapped to a linear arrangement on the backplane.
Using this setup we are able to run Linux on each NATHAN locally and have fast cross linking among the NATHANs to buid up a scalable, distributed system .

Fast edge rates and the high integration density on the NATHAN modules require controlled impedance structures all over the system to avoid transmission line effects like reflection and crosstalk. All critical nets have been simulated and their signal integrity could be verified prior to production. First measurements with the MGTs have shown that we are able to achive the full bandwidth of 3.125Gbps over a length of 50cm FR-4 and two connectors. The picture on the left shows an eye diagram of a transmission over this longest possible distance on the backplane.

Currently, we are testing the first four NATHANs with two XC2VP4 and two XC2VP7 FPGAs. The results show that all specifications have been fullfilled and the system should be up and running soon.
Feel free to get some impressions of the system in the gallery.

 

NATHAN features

Chipset

  • Xilinx Virtex-II Pro FPGA (XC2VP4 or XC2VP7)
  • SO-DIMM socket for up to 1GB of DDR-SDRAM
  • 1 MB S-RAM
  • 1 MAX5253 quad 12Bit DAC
  • Temperature sensor to monitor FPGA and HAGEN temperature

Input/Output

  • up to eight 3.125Gbps full duplex serial links
  • ErmetZD differential high speed connector to carry Gigabit signals
  • up to four 8Bit wide Hypertransport channels on daughter card

Technologies:

  • 8 layer buid-up MicroVia Design (Wuerth Elektronik)
  • 672 Pin Finepitch BGA-Package for FPGA
  • FPGA boundary scan (JTAG) support

Backplane features

Chipset

  • 2 Epson EG-2101 high precision clock oscillators for local clock generation
  • 1 MAX9112 LVCMOS to LVDS transceiver
  • 4 Texas Instruments PT-8001 high current switching power supplies
  • 16 MAX1809 DDR termination power supplies
  • 16 LM1083 linear regulators

Input/Output

  • 1 68Pin differential SCSI connector to connect to darkwing (i.e. control PC).
  • ErmetZD differential high speed connector to carry Gigabit signals

Technologies:

  • 4 layer standard FR-4 design (Wuerth Elektronik)
Last update of this page: 2011-05-19_