Waferscale Integration Methods

One aim of the FACETS project is to achieve wafer scale integration of analog neural networks. This allows the implementation of network sizes beyond the limitation of a single reticle, which is restricted to 25 x 25 mm² in the used process.

To be able to use the whole wafer area for the realization of the analog circuits representing the neurons and synapses, the wafer has to be left uncut and the single chips on the wafer have to be connected to each other. Therefore anadditional processing steps have to be done after the wafer fabrication. The so called post processing is used to connect the single chips with a very high connection density.

• Wafer Postprocessing
• System Design and Mechanics