Current research focuses on the following topics:

  • FPGA-Reconfiguration/Hardware Objects
    Many of today's software-to-hardware compiler projects try to find dataflow parallelism in a sequential program description and use it to generate parallel running hardware components. We want to present a new possibility to do a parallel description based on the combination of object-oriented programming (OOP) and dynamically partial reconfiguration (DPR). Our compiler translates software objects directly to Hardware Objects, which are running in parallel and can be instantiated and removed dynamically. The main target of this concept is to use the potential intrinsic parallelism of OOP. For this we introduce a new, Java based language: POL (Parallel Object Language).
  • HLT Status Visualization

  • SysMES HLT Management
  • FPGA Fault Tolerance in Particle Physics Experiments
    fault tolerance chain
    The increasing use of SRAM-based reconfigurable architectures at important areas of research and development like particle accelerators and space applications brings new, currently partially unattended effects on top. An already well known, but nevertheless important problem of such systems is its susceptibility to radiation which increases in conjunction with particle flux and energy. Unable to prevent these bit failures by the use of extensive shielding, our field of research is to use intelligent algorithms and redundancy features to eliminate each of such effects that may cause a Single Event Functional Interrupt (SEFI) which leads to miscalculation, system failure or an entire system halt.

Last update of this page: 2010-06-15_