Circuits and methods for VLSI design: Weekly seminar of the Heidelberg ASIC-Laboratory

We meet in the Seminarbox (1.107) at the first floor at 16:00 s.t.

Next seminar will be on: 16.5.2012

• Mu3e detector based on HV-MAPS - Dirk Wiedner

Topics for other seminars

• Lecroy oscilloscope presentation - 6.6.2012

Previous seminars

25.4.2012

• Wireless transfer: Towards a 60 GHz Multi-Gigabit System-on-Chip - Hans-Kristian Soltveit

18.4.2012

• MMC Results - Sebastian Millner, Andreas Hartel

11.4.2012

• Measurement results TSMC 65nm Testchip - Jakob Kunz

4.4.2012

• Design Review STiC2v1 LVS - Tobias Harion

28.3.2012

• Design Review STiC2v1 Overview - Tobias Harion

7.3.2012

• Leakage Current in 65nm Custom SRAM/Capacitive Analog Memory, Part 2 - Matthias Hock

15.2.2012

• Results wafer assembly - Andreas Grübl

8.2.2012

• Simulating chips with brICk - Andreas Hartel

1.2.2012

• A USB-based FPGA platform for Neuromorphic ASICs Part 2/Software stack - Johannes Schemmel

25.1.2012

• Results TSMC 65nm Testchip V2 - Matthias Hock and Simon Friedmann

18.1.2012

• STIC2 results - Tobias Harion

11.1.2012

• Floating Gate Introduction - Sebastian Millner

19.12.2011

• Talk about mismatch in a 65nm process - Christian Graf (Slides)

14.12.2011

• A Digital Design for the ATLAS Pixel DCS - Jenny Boek and Lukas Püllen (Slides)

7.12.2011

• Deep submicron noise problems - Wei Shen (Slides)

23.11.2011

• A USB-based FPGA platform for Neuromorphic ASICs Part 1 - Johannes Schemmel

16.11.2011

• KLauS2 measurements - Wei Shen (Slides)

9.11.2011

• Plasticity Processor Version 2 - Simon Friedmann (Slides)

2.11.2011

• After submission MMC report - Sebastian Millner & Andreas Hartl

26.10.2011

• HICANN wafertest - Andreas Grübl

12.10.2011

• LeCroy ArbStudio - H. Fischer (Admess)

28.9.2011

• Submission Readiness Review TC65NM Version 2 - Matthias Hock & Simon Friedmann

21.9.2011

• Submission Readiness Review MMC - MultiCompartmentChip - Sebastian Millner & Andreas Hartel

17.8.2011

• TSMC 65nm Testchip Measurement Results - Matthias Hock

10.8.2011

• Indroduction Current Conveyor/Design Considerations for Multi-Compartment Neurons part 3 - Sebastian Millner

20.7.2011

• Design Considerations for Multi-Compartment Neurons part 2 - Sebastian Millner

13.7.2011

• Presentation STiC 2.0 (TOFPET project) part 2 - Tobias Harion

6.7.2011

• Presentation STiC 2.0 (TOFPET project) part 1 - Wei Shen

29.6.2011

• Design Considerations for Multi-Compartment Neurons part 1 - Sebastian Millner

20.6.2011

• Design Readiness Review - Wei Shen

8.6.2011

• HICANN Testresults/Wafer Readiness Review - Andreas Grübl

1.6.2011

• Europractice course "Power-Aware Design" - Andreas Hartel

18.5.2011

• Mixed-Signal simulation with bi-directional interface elements - Andreas Hartel

20.4.2011

• Cadence Information Day at Tuebingen: "Transaction based modeling and synthesis" - Andreas Grübl

13.4.2011

• Timing Closure in a 65nm process - Andreas Hartel (Slides)

6.4.2011

• "ESD protection circuits - High voltage measurements" -  Marc-Olivier Schwartz (Slides)

30.3.2011

• Readiness review TSMC 65nm Testchip

16.3.2011

• Measurement results from Klaus2

9.3.2011

• Short introduction into Leda, Formality and Encounter Power System (ETS)

2.3.2011

• Discussion about 65nm Testchip for the TSMC process managed by Matthias

16.2.2011

• Talk from Simon about Micro Processor with a Power Architecture (Slides Part 2)

9.2.2011

• Talk about Micro Processor with a Power Architecture - Simon Friedmann (Slides Part 1)

19.1.2011

• Planning testchip in TSMC 65nm

12.1.2011

• "Neujahrsansprache" from Johannes :-)
• Happy New Year

15.12.2010

• Bonding talk from Ralf (Slides)

8.12.2010

• "ASIC design flows and verification with waf"

1.12.2010

• Abstract generation von Andreas Gruebl

24.11.2010

• LVS/DRC/ANT Probleme und Loesungen zum KLausV2 Design

27.10.2010

• SystemC/Verilog/VHDL/... Simulation

20.10.2010

• Monte Carlo Simulationen "LIVE"
• TSMC SRAM Macros

13.10.2010

• Chip Design Review - Wei Shen