Schaltungen und Methoden im VLSI Design: Wöchtliches Seminar des ASIC Labors Heidelberg

Wir treffen uns in der Seminarbox I (01.107) im 1.Stock um 16:00 s.t.

Vorträge

31. Mai 2017
21. Juni 2017
16:00 Uhr ASIC: TBA... Konrad Briggl
5. Juli 2017
16:00 Uhr ASIC: First results of HICANN-DLS measurements... Gerd Kiene, Korbinian Schreiber, Sebastian Billaudelle, Yannik Stradmann

Bisherige Vorträge

10.05.2017

  • BrainScales 2: A Novel Architecture for Analog Accelerated Neuromorphic Computing Including Hybrid Plasticity - Dr. Johannes Schemmel (Slides)

26.04.2017

  • Impressions and pictures from Yxlon visit - Ralf Achenbach (Owncloud PW can be request from me)

29.03.2017

  • Novel And Exotic Packaging And Test Equipment - Ralf Achenbach (Slides)

22.03.2017

  • Depleted Monolithic Active Pixel Sensors - Heiko Augustin @HighRR-Seminar (Slides)

08.03.2017

  • Bumping and flip chip of ASICs - Dr. Christian Kreidl @HighRR-Seminar (Slides)

15.02.2017

  • A fully differential analog neuron study - Gerd Kiene (Slides)
  • Render GDS into 3d - Gerd Kiene (GDS3D based on gds2pov)

01.02.2017

  • Self-biased PLL design and noise analysis - David Schimansky (Slides)

18.01.2017

  • Updates on the KLauS ASIC for ILC - Zhenxiong Yuan (Slides)

11.01.2017

  • New memory architecture for upcoming HICANN-DLS-SR - Christian Pehle (Slides)
 
zum Seitenanfang
Vorträge
31. Mai 2017
21. Juni 2017
16:00 Uhr ASIC: TBA... Konrad Briggl
5. Juli 2017
16:00 Uhr ASIC: First results of HICANN-DLS measurements... Gerd Kiene, Korbinian Schreiber, Sebastian Billaudelle, Yannik Stradmann
ASIC Bilder