Under experiment conditions the sampling clocks sensitive edge (i. e. the falling edge) would be placed right on the signal's peak. The comparators' sensitive edge (i. e. the rising edge) a bit thereafter (e. g. 5ns) to ensure that the switching of the comparators' output does not disturb sampling the analog signal.
In the test setup the sampling clock was shifted with respect to the
test pulse (and thus the pulse shape). The comparator clock's rising edge
was placed at the time indicated by the vertical bars. Test signals were
injected into 5 channels of different groups of 4 comparators, thus 4 comparators's
outputs switched (as was observed). Thus 5 x 4mA were driven into the chip,
which is a realistic situation.
A crosstalk of the comparators#s output to the analog signal can still
be seen, but the peak is (of course) not seen before the comparator switch
and it decays until the next sampling.